RISC-V CPU

For Berkeley's CS 61C, I built a complete RISC-V CPU in Logisim — a digital logic simulation tool. The project starts at the transistor level and builds up to a functioning processor capable of executing a real instruction set.

Architecture

Datapath: ALU supporting the full RISC-V RV32I integer instruction set. Register file, immediate generator, branch comparator, and control logic implemented from combinational logic primitives.

Pipelining: 5-stage pipeline — Instruction Fetch, Decode, Execute, Memory, Writeback. Implemented hazard detection logic for data hazards (with forwarding to minimize stalls) and control hazards (branch prediction with flush on misprediction).

Memory hierarchy:

• L1 instruction and data caches with configurable size and associativity
• L2 unified cache
• DRAM simulation with realistic access latency

Virtual memory: TLB for address translation caching. Page table walker in hardware for TLB misses.

Why Logisim

Logisim is painful. Everything is drag-and-drop wires. When a signal is wrong, you trace it manually gate by gate. But that pain is the point — you can't cargo-cult your way through it. By the end I had a visceral understanding of why pipelines stall, why cache misses hurt, and why branch mispredictions are expensive. Those intuitions have stayed with me through every systems course and role since.